1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly to a Metal Oxide Semiconductor Field Effect Transistor (called hereunder, MOSFET) having a non-uniformly doped submicron channel length and L-shaped side wall extensions.
2. Description of the Prior Art
Recently, MOS transistors have been rapidly scaled down, involving shortened channel lengths thereof. This results in severe degradation of electrical characteristics of MOS transistors due to threshold voltage lowering and mobility degradation when the channel length becomes comparable to the source and drain regions depletion layer width. These effects are known as "short-channel degradation", and are a serious limitation for further device scaling.
Some approaches for overcoming the above effects are known. One of these approaches adopts the so-called "halo" or "pocket" deep implantation to provide highly doped regions 23 and 24 near the respective junctions of source 21 and drain 22 of a MOS transistor 20, as shown in FIG. 6 (C. F. Codella and S Ogura, "Halo doping effects in submicron DI-LDD device design", IEDM Tech. Dig. (1985), 230). However, the depth and lateral spread of this implantation may be limited in sub-half micrometer channel length transistors, and in addition, a higher doping concentration at the drain junction increases the junction parasitic capacitance, degrading device speed.
Another approach uses oblique rotating ion implantation to form a non-uniformly doped channel of a MOS transistor 30, as shown in FIG. 7 (Y. Okumura, et al.: "A Novel Source-to-Drain Nonuniformly doped Channel (NUDC) MOSFET for high current drivability and threshold voltage controllability", IEDM Tech. Dig. (1990), 391). According to this technique, the doping concentration is higher near the source and drain, which reduces the widening of the depletion region, and at the same time, the doping concentration in the middle of the channel is reduced to improve the carrier mobility. The limitation of his technique is that in order to penetrate about 1/3 of the channel length, a relatively large implantation angle (Q) and a relatively high energy are required. This results in: (i) higher concentration at the drain junction, degrading device speed; and (ii) difficult control of the channel middle region width, especially in sub-half micrometer devices.
Still another approach employs the GOLD (Gate Over-lapped LDD) or the Inverse T gate structures in submicron channel MOSFET, which is very convenient to reduce Hot-Carrier induced degradation.
As is seen from FIG. 8, in the GOLD structure, a gate oxide layer 42, a polysilicon layer 43, a silicon oxide layer 44 and a polysilicon layer 45a are laminated in sequence on a silicon substrate 41. Subsequently, the polysilicon layer 45a is etched to form a gate electrode 45. Using the gate electrode 45 as a mask, ions are implanted to form N.sup.- regions. Then, a polysilicon 46a is disposed thereon and a side wall 46 is obtained by etching. Next, using the side wall 46 as a mask, ions are implanted to form N.sup.+ regions (Symposium on VLSI Technology, p49 (1991). Apparently, the LDD regions must be completely under the gate electrode 45 in order to improve the transistor strength against Hot-carriers. However, this structure requires the lamination of three polysilicon layers, resulting in a complex fabrication process.